1. Field of the Invention
The present invention relates to apparatus and methods for depositing and etching films on semiconductor substrates for integrate circuits, and more particularly is related to a method for improving the reactant gas flow distribution in a process chamber for more uniform deposited film and more uniform etch rates.
2. Description of the Prior Art
Chemical Vapor Deposition (CVD) of films and patterning of films using photolithographic techniques and plasma etching (dry etching) are used extensively by the semiconductor industry for fabricating integrated circuits on semiconductor substrates. The deposition and etching processes are performed in either a batch or single-wafer reactive chamber. However, because of the increase in the diameter of the substrate over the years, the trend in the industry is to single-wafer chamber processing. For example, improvements in the growth of single crystal silicon ingots, usually by the Czochralski method, the wafer cut from the ingot have increased significantly over the past years. For example, in the early 1970's the wafer were only about 1.25 inches in diameter, and currently wafers having a 6.0 inch diameter are commonly used in semiconductor manufacturing lines. By the year 2000 the wafer diameter is expected to double to about 12 inches. For these larger wafers the trend in the semiconductor industry is to use single-wafer processing (reactive) chambers which have economic and other practical advantages. For example, the single-wafer chambers can be clustered around a single vacuum load-lock system to provide a sequence of processing steps without exposing the chamber or wafers to the ambient. These cluster systems are also easier to automate than the batch-wafer chambers. FIG. 1 shows a simplified schematic top view of a cluster system in which three single-wafer process chambers A, B and C are attached to the load-lock 3. The wafer are automatically loaded from cassette 1 in the portion the load-lock area 6 into the single-wafer chambers by the mechanical arm 4. Shown in FIG. 1 are wafers 10 and 11 loaded in chambers A and B, respectively and wafer 12 still on the transport mechanism 4 about to be loaded onto the substrate electrode 7 in chamber C.
When the single-wafer chamber are used in the conventional plasma etch mode, (FIG. 2) the etchant gas mixtures 32 are distributed in the chamber through a gas distribution system, such as the shower head 32 shown in FIG. 2. That distributes the reactant gas evenly over the wafer. The shower head 32 also serves as the top electrode to which is applied radio frequency (RF) power from a generator 36 through an impedance matching circuit 35. The substrate electrode 7 is usually electrically grounded, and water cooled. Alternatively, another method of etching with a plasma is in the reactive ion etch (RIE) mode. As shown in FIG. 3, in the RIE mode the top electrode is electrically grounded and the RF power is applied to the substrate electrode 7 using the RF generator 36 and impedance matching circuit 35 to generate the plasma. A blocking capacitor 40 is also used in series with the matching circuit 35 to provide the self-biasing (DC) voltage on the substrate electrode 7 for the directional etching. The wafer 10 on the substrate electrode 7 is usually kept cool by cooling the electrode with water.
When a single-wafer reaction chamber is used to deposit a film by chemical vapor deposition (CVD) on a wafer, the substrate electrode is electrically grounded an thermally heated, such as by a resistive element in the substrate electrode, as depicted in FIG. 4, or by radiant heating through a quartz window. The reactant gas used for deposition is also distributed through a shower head 32 uniformally across the wafer 5 on the substrate electrode 7, also shown in FIG. 4. Typically in the low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) mode the film deposition on the wafer is reaction rate limited at the wafer surface, and is therefore strongly dependent on the wafer temperature. Also, non-uniform gas phase concentrations produced by local depletion of the reactant gases can result in non-uniform deposition, especially at asymmetries on the wafer, such as at the wafer flat.
It is important that the chemical vapor deposited films and the dry etch process are uniform across the wafer in these single-wafer process chamber so as to avoid over-etching the underlying layer when the layer is patterned. For example, in todays high density semiconductor circuits having field effect transistors (FETs), the gate electrode is usually patterned from a polysilicon or silicide layer which is deposited to a thickness of between 2000 to 4000 Angstroms over a very thin gate oxide which is usually less than 100 Angstroms. Therefore, excessive over etching because of non-uniform layers or/and non-uniform etching can damage the device structures in the over etched regions on the wafer, thereby reducing chip yield. Critical device dimensions, such as FET channel lengths under the gate electrode (now less than 0.5 um) can also be effected by excessive over etch which can increase the etch bias.
Unfortunately, during processing the deposition uniformity for the LPCVD and the etch uniformity are also effected by the wafer shape. More specifically the flat that is formed along the ingot to identify the specific crystal direction, and is used to align the wafer during photolithographic exposure and automatic wafer handling can also perturb the deposition and etching rates during processing resulting in non-uniformities. Therefore, there is still a strong need in the semiconductor industry to provide a method for improving the LPCVD deposition and plasma etching uniformity during wafer processing.